When constructing static random access memories (RAMs), it is desirable to increase the speed at which memory locations are accessed and their data read, while reducing total power consumption of the memory array and accessing circuitry. To accomplish both goals , the data stored at a particular memory location should be sensed as quickly as possible after that location is initially addressed. This is usually accomplished by sensing a voltage drop on one of the complementary high/low outputs of the data output lines of a memory array column.
Operating speed is increased and power consumption is reduced specifically by sensing the voltage drop at the data output lines well in advance of their complete voltage drop. The voltage drops relatively slowly in a large array owing to the inherent capacitance of the memory cells, which presents significant impedance on row word lines and column bit lines. Thus the sensing may occur when only a few hundred millivolts of voltage drop have actually occurred. This small drop is subsequently amplified to a full logic state voltage (e.g., 0 or 5 volts) by an in line sense amplifier.
A significant problem with such a voltage drop sensing system is that timing of the sense amplification operation must be very accurately controlled. If the sensing occurs too soon, the voltage drop may not be sufficient, or stable enough, to guarantee a reliable reading of the prevailing logic state in the presence of the inherent electrical noise. Similarly, if the voltage drop sensing function occurs too late, a significant amount of extra power and time may be wasted in acquiring the data signal. As microcircuits become larger and operated at higher clock rates, it becomes even more important to avoid such waste.
In the past, sense enable timing has particularly been accomplished by providing a sense enable signal to a sense amplifier connected to the data output lines. The sense amplifier senses the data output lines only upon receiving the sense enable signal. The timing of this sense enable signal is based upon the delay in the propagation of the row address signal and the additional propagation time of a data value down the column bit lines. In the prior art sense enable signal operating circuit of FIG. 1, the assertion of a sense enable signal SE is delayed by the combined propagation delays of a long series of inverters 15, connected from a RAM precharge or other word line enabling signal (WORD LINE ENABLE) 16. With adjustments for this inherent delay and other particular array characteristics, the delay circuit roughly approximates the time required to attain a stable signal at the input of a sense amplifier.
However, the semiconductors produced by various manufacturers, as well as the batches of a given manufacturer, may be highly variable in their operating characteristics. This is particularly true relative to the speed of operation and curves of voltage output versus time for data output signals. As such, while a delay scheme such as that shown in FIG. 1 may work well for the array of one manufacturer, it may prove wasteful or wholly inoperative when used with another manufacturer's semiconductors owing to their differing operating rates or output voltage versus time curves. It may also be desirable to employ differing transistor technologies such as NMOS or gallium arsenide.
Therefore, in order to use the FIG. 1 scheme while optimizing the timing of the sense enable function, it would be necessary to tailor the delay circuit to each semiconductor manufacturers processing and even to various batches of the same manufacturer. Clearly, given the cost of masking and manufacturing a mass produced semiconductor chip, this is not practical. Thus, as a practical matter, all the circuits must be tailored to the slowest functioning components that are anticipated.